1. Field of the Invention
The present invention relates to a data processor allowing a high speed access, and more specifically to a slave processor adapted to execute a read/write operation in response to a read/write request from a master processor, the slave processor having a wait control allowing a high speed operation of the master processor particularly in the write operation.
2. Description of related art
Conventionally, in so-called master-slave processor systems, when a master processor dispatches a read request or write request to a slave processor, operation will be executed in the following sequence:
In the case of read operation, the master processor activates a read request signal to the slave processor. Immediately upon receipt of this active read request signal, the slave processor starts a read operation. On the other hand, the master processor is required to continue to maintain the read request signal in an active condition until the slave processor has completed preparation of a read data. The reason for this is that the master processor has to receive the data before it makes the read request signal inactive, and on the other hand, the slave processor requests the master processor to wait until the slave processor completes the preparation of a read data. This wait operation is controlled by a so-called wait signal or read signal. Namely, the slave processor will maintain the wait signal as active until it prepares the read data, and the master processor will maintain the read request signal in an active condition until the wait signal is rendered inactive.
A write operation is performed similarly to the sequence of the read operation mentioned above, except for the active period of a wait signal. Namely, in the case of a write operation, the wait signal is maintained active until the slave processor completes the writing of data inputted from the master processor. This purpose is to maintain the data to be written to the slave processor by the master processor without any change. Therefore, the master processor is required to continue to maintain the write request signal active in a period corresponding to the active period of the wait signal.
As will be apparent from the above description, the conventional wait control is disadvantageous in that an access time of the master processor to the slave processor will inevitably become long in the case that the slave processor needs a long time of read data preparation or a long time of data write operation. Particularly, the larger the frequency of accesses to the slave processor is, the operation speed of the overall master-slave processor system will become lower.